Ever since the introduction of the microprocessor, computer systems have been getting faster and faster. In approximate accordance with Moore's law (based on Intel® Corporation co-founder Gordon Moore's 1965 publication predicting the number of transistors on integrated circuits to double every two years), the speed increase has shot upward at a fairly even rate for nearly three decades. At the same time, the size of both memory and non-volatile storage has also steadily increased, such that many of today's personal computers are more powerful than supercomputers from just 10-15 years ago. In addition, the speed of network communications has likewise seen astronomical increases.
Ever increasing speeds have produced more powerful processors and devices employing the processors (such as PCs, servers, workstations, and mobile devices). More powerful in more ways than just processing power—these processors and devices also consume more power. Higher power consumption is undesirable on several fronts. First, it leads to increased die temperatures, reducing processor life. For line-powered computers, such as PC's and servers, increased power results in higher energy bills. In high-density server deployments such as server farms and data centers, small increases in power on a per server basis result in huge increases in power consumption and resulting costs for the deployment (and conversely, small power reduction on a per server basis result in significant cost savings). Power consumption is a huge factor in mobile device performance. For example, an engineer could design a mobile device with processing power equal to a high-end server; however, such a device would have such a short battery life that it would be unacceptable for commercial uses.
There are various techniques for reducing power in computers and other processor-based devices. A common technique is to put the processor into a reduced power state (aka idle states or sleep states) when it isn't being actively used. Recently introduced multi-core processors support the ability to put processor cores into selected idle states on an individual core basis. There are even power control techniques that apply to a processor as a whole. For example, microprocessor performance states (P-States) are a pre-defined set of frequency and voltage combinations at which the microprocessor can operate when the CPU is active. The microprocessor utilizes dynamic frequency scaling (DFS) and dynamic voltage scaling (DVS) to implement the various P-States supported by a microprocessor. DFS and DVS are techniques that dynamically changes the operating frequency and operating voltage of the microprocessor core based on current operating conditions. Thus, power savings can be effected across a processor by changing its P-State. Package power states (e.g., Pck C-States) may also be applied the processor level to significantly reduce power. Power saving techniques can also be applied at the overall platform level, resulting in further savings.
Most of these approaches target power savings at a particular component or set of components (e.g., cores or the uncore). However, there is still a significant portion (˜10% to 30%) of the platform power consumed by various interconnect fabric and links, both within the processor die and between the processor and other platform components. Interconnect fabric consists of routers, ports and links, with the ports and associated links consuming non-negligible amount of power (˜70% of the router power). In order to reduce the holistic platform power consumption multiple link low power states are defined and implemented to achieve link power saving.
In the PCIe Specification, various power saving states are provided for a link (i.e., an interface) of a serial interconnect. Specifically, the specification describes the presence of link states L0, L0s, L1, L2 and L3. The L0 state corresponds to link on and the L2 and L3 states correspond to link off (with the difference being that auxiliary power is present in the L2 state), while the L0s state provides for a low-resume standby latency state, and the L1 state corresponds to a low power standby state. These low power states may be achieved via the Active Status Power Management (ASPM) capability of a PCIe interface, which enables an endpoint device to request entry into a low power state. In general, as the link power state is lowered, additional power savings is realized; however, the lower the power state, the larger the exit (link resume) latency to return the link back to an active state. Similar power states are also defined for other fabrics and interconnects such as IOSF (Intel on-chip System Fabric) and Thunderbolt®.